The present invention relates to a process for manufacturing a semiconductor integrated circuit device and, more particularly, to a technique for exposing semiconductor regions over the surface of a semiconductor substrate in self-alignment to wiring lines (including gate electrodes) and element isolating regions when connection holes are to be formed in a flattened layer insulating film.
As a first technique, the SAC (Self-Aligned Contact) technique for forming connection holes in a layer insulating film covering gate electrodes and in self-alignment with the gate electrodes is described on pp. 1864 to 1869 of IEEE Transaction ED-43, No. 11 (1996), for example. Here is disclosed a technique in which the gate electrodes are constructed to have the so-called "poly-metal structure", which means that a refractory metal film is laminated over a low-resistance poly-silicon film through a barrier metal film, and a cap insulating film over the gate electrodes and a side wall insulating film on the sides of the gate electrodes are formed of a silicon nitride film.
According to this technique, when the connection holes are to be formed in the layer insulating film of a silicon oxide film, they can be formed in self-alignment with the gate electrodes by etching them selectively with respect to the silicon nitride film. This makes it unnecessary to take a margin between the gate electrodes and the connection holes so that the size of a MISFET can be reduced to increase the number of MISFETs to be packaged in a chip of a predetermined size thereby to raise the degree of integration.
Here, as seen from the aforementioned first technique, the main flow is the element isolation structure (as called the "trench isolation") in which the element isolating insulating film made of a thermally oxidized film is replaced by the trenches formed in the surface of the semiconductor substrate and buried with a CVD oxide film or the like.
In the case of the aforementioned first technique, a margin has to be so retained between the opening of a photoresist mask and the element isolating regions that the opening of the mask does not extend over the element isolating regions when the connection holes are to be formed. If the opening of the photoresist mask extend over the element isolating regions, the oxide film in the trenches will also be etched at the time of etching the layer insulating film thereby to cause a danger of conduction between the semiconductor regions and the substrate.
Thus, it is needless to say that the retention of the margin between the mask opening and the element isolating regions raises a cause for preventing the size reduction of the MISFETs.
Although not well known in the art, on the other hand, here will be described a second technique (Japanese Patent Application No. 92608/1997) for forming the connection holes in self-alignment with the gate electrodes but without any margin from the element isolating regions.
In this second technique, a cap insulating film formed of only a silicon nitride film is formed over the gate electrodes, and the principal face of a semiconductor substrate, the side faces of the gate electrodes and the surface (including the side faces and the upper face) of the cap insulating film are coated with a thin silicon nitride film. In this second technique, the aforementioned connection holes for exposing the semiconductor substrate are formed at first by performing an etching treatment under such a condition that a layer insulating film made of a silicon oxide film is more easily etched off than the silicon nitride film, and when the thin silicon nitride film is exposed, by performing an etching treatment under such a condition that the silicon nitride film is more easily etched off than the layer insulating film. According to this second technique, it is possible to solve the problem that even if a silicon oxide film of the same kind as that of the layer insulating film is buried in the element isolating regions formed in the semiconductor substrate, the silicon oxide film buried in the element isolating regions is etched to establish the conduction between the semiconductor regions and the substrate at the time of forming connection holes.